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The Magic of RISC-V Vector Processing
Implementation of an Out-of-order RISC-V Vector Unit- Roger Espasa, SemiDynamics Technology Services
Digital Design and Comp. Arch. - Lecture 19: SIMD Architectures (Vector and Array Processors) (S23)
The RISC-V Vector Cryptography Extensions - G. Richard Newell & Ken Dockser
SiFive Vector AI Processors Accelerated by the RISC-V Vector ISA by Vadim Malenboim, SiFive
RISC-V VSI-EA: Evaluation of Vector & SIMD ISA Instructions for embedded applications -BTU & Codasip
The Real Challenge for RISC-V Vector Processors - John Min, Andes Technology
An Introduction to RISC-V Vector Programming with C Intrinsics - Chih-Mao Chen, Andes Technology
limitations of mis-named Scalable Vector ISAs
Lightning Talk: Software Development for ML and RISC-V Vector Acceler... Lee Moore & Simon Davidmann
Next-Generation Vector Processor Design III
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Last Updated: August 11, 2026
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