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6B1 Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-in-Memory Architectures
SparseP: Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Architectures
LIKWID, OSACA, and Sparse Matrix-Vector Multiplication (SpMV) on the A64FX Processor
Parallel sparse matrix vector multiplication
Performance Engineering for Sparse Matrix-Vector Multiplication with RACE
Communication-Avoiding and Memory-Constrained Sparse Matrix-Matrix Multiplication at Extreme Scale
Bandwidth-Optimized Parallel Algorithms for Sparse Matrix-Matrix Multiplication using Propagation Bl
[MICRO'20] MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product
SpArch: Efficient Architecture for Sparse Matrix Multiplication, [HPCA 2020]
A Fully Structure-driven Performance Analysis of Sparse Matrix-vector Multiplication
LHAM:161 Improving the Accuracy in SpMV Implementation Selection with Machine Learning
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Last Updated: August 18, 2026
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![[MICRO'20] MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product](https://i.ytimg.com/vi/9D4MkxqG3ac/mqdefault.jpg)
![SpArch: Efficient Architecture for Sparse Matrix Multiplication, [HPCA 2020]](https://i.ytimg.com/vi/s9ABFm9TRUI/mqdefault.jpg)
